Cirrus Logic EP93xx User Manual

Page 595

DS785UM1

16-19

UART3 With HDLC Encoder

EP93xx User’s Guide

RAB:

Receiver Abort. (Read Only)
0 - No abort has been detected for the incoming frame.
1 - Abort detected during receipt of incoming frame. The
most recently read data is the last valid data before the
abort. EOF is also set.

Note: This bit reflects the status associated with the last character read from the RX FIFO. It

changes with reads from the RX FIFO.

RTO:

Receiver Time Out.
Set to “1” whenever the HDLC RX has received four
consecutive flags, or four character times of idle or space.
Cleared by writing a “1” to this bit.

EOF:

End of Frame (read only).
0 - Current frame has not been received completely.
1 - The data most recently read from the RX FIFO is the
last byte of data within the frame.

Note: This bit reflects the status associated with the last character read from the RX FIFO. It

changes with reads from the RX FIFO.

RFL:

Receive Frame Lost. (Read/Write)
Set to “1” when an ROR occurred at the start of a new
frame, before any data for the frame could be put into the
RX FIFO. Cleared by writing a “1” to this bit.

RIL:

Receive Information buffer Lost. (Read/Write)
Set to “1” when the last data for a frame is read from the
RX FIFO and the UART1HDLCRXInfoBuf has not been
read since the last data of the previous frame was read.
That is, the information loaded into the
UART1HDLCRXInfoBuf about the previous frame was
never read and has been overwritten. Cleared by writing a
“1” to this bit.

RFC:

Received Frame Complete. (Read/Write)
Set to “1” when the last data byte for the frame is read
from the RX FIFO (this also triggers an update of the
UART1HDLCRXInfoBuf). Cleared by writing to a “1” to this
bit.

RFS:

Receive FIFO Service request. (Read Only)
This bit is a copy of the RIS bit in the UART interrupt
identification register.
0 - RX FIFO is empty or RX is disabled.
1 - RX FIFO not empty and RX enabled.
May generate an interrupt and signal a DMA service
request.