Cirrus Logic EP93xx - Manual (Page 368)

9-66 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
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PHYAD: PHY Address. This field defines which external PHY is to
be accessed.
REGAD: Register Address. This field defines the particular register
in the PHY to be accessed.
MIIData
Address:
0x8001_0014 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
MII Data Transfer Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
MIIData: MII Data Register. This register contains the 16 bit data
word that is either written to or read from the appropriate
PHY register.
MIISts
Address:
0x8001_0018 - Read Only
Chip Reset:
0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIIData
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD BUSY