2 pixelmode, 11 blink logic, 1 blinkrate – Cirrus Logic EP93xx User Manual

Page 214: 2 defining blink pixels, 2 pixelmode -32, 11 blink logic -32, 1 blinkrate -32 7.4.11.2 defining blink pixels -32

7-32

DS785UM1

Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide

VLineStep = 640 x 4bpp/32

7.4.10.2 PixelMode

Pixel data is transferred from the FIFO to the Video Pixel Mux two 32-bit words at a time (total
of 64 bits). Bits[2:0] of the

“PixelMode”

Table 7-

. The Video Pixel MUX uses the

“PixelMode”

contained in the 64 bits of data. The Video Pixel Mux extracts pixel data from the 64-bits and
passes that pixel data to the BLINK logic one pixel at a time.

Note: All other combinations for these three bits are illegal.

7.4.11 Blink Logic

The blink logic facilitates blinking of individual pixels as they move through the video pipeline.
The blink frequency is controlled by the

“BlinkRate”

same rate.

7.4.11.1 BlinkRate

This value is used to control the number of video frames that occur before the pixel value that
is assigned to blink is switched between its non-blinked and blinked values. The actual rate is
calculated by:

Blink cycle = 2 x (1 / VCLK) x HClkTotal x VLinesTotal x (255 - BlinkRate)

where:

VCLK is the basic clock rate of the video logic

HClkTotal is the value contained in the

“HClkTotal”

VLinesTotal is the value contained in the

“VLinesTotal”

BlinkRate is the value contained in the

“BlinkRate”

7.4.11.2 Defining Blink Pixels

A blink pixel must be defined before the blink logic is applied to a given pixel. The

“BlinkPattrn”