Hclktotal, Hsyncstrtstop, Horizontal frame timing registers hclktotal – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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Horizontal Frame Timing Registers
HClkTotal
Address: 0x8003_0010
Default: 0x0000_0000
Definition: Total pixel clocks that compose a horizontal line
Bit Descriptions:
RSVD:
Reserved - Unknown during read
TOTAL:
Total - Read/Write
The HClk Total timing register contains the total number of
clocks for a horizontal video line including synchronization,
blanking, and active clocks. This value is used to preset
the Horizontal down counter. Please refer to video
signalling timing diagrams in
HSyncStrtStop
Address: 0x8003_0014
Default: 0x0000_0000
Definition: HorizontaL Sync Start/Stop Register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
31
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RSVD
15
14
13
12
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10
9
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3
2
1
0
RSVD
TOTAL
31
30
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19
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16
RSVD
STOP
15
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4
3
2
1
0
RSVD
STRT