Cirrus Logic EP93xx - Manual (Page 431)

DS785UM1 10-37
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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STATUS
Address:
Channel Base Address + 0x000C - Read/Write
Definition:
This is the channel status register, used to provide status information with
respect to the DMA channel. All register bits are read-only except for the
DREQS status bit which can be cleared by a write (either a “0” or a “1”) to this
register.
Write this location once to clear the interrupt (see Interrupt Register Bit
Descriptions for which bits this rule applies to).
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
Stall: A “1” indicates channel is stalled and cannot currently
transfer data because the START bit has not been
programmed or an external device has not asserted
DREQ. When the channel is first enabled, the Stall bit is
suppressed until the first buffer has been transferred, that
is, no stall interrupt generated when STALL state entered
from IDLE state, only when entered from MEM_WR State.
The STALL state can be cleared by:
•Setting the START bit
•An external peripheral requesting service (depending on
transfer mode)
•Disabling the DMA channel
•A request from SSP or IDE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD DREQS NB NFB EOTS TCS DONE CurrentState STALL