Cirrus Logic EP93xx - Manual (Page 422)

10-28 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
1
0
1
0
10
REMAIN
Address:
Channel Base Address + 0x0014 - Read Only
Definition:
The Channel Bytes Remaining Register contains the number of bytes
remaining in the current DMA transfer. Only the lower 16 bits are valid
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
REMAIN: Loaded from the Channel MAXCNT register when the
DMA Channel State Machine enters the ON State.
Although there are 2 Data transfer states, ON and NEXT,
this register need only be assigned in the ON state,
because in this state the next buffer to be used is
determined (there is only one) and this MAXCNT value is
assigned to REMAIN. The DMA State Machine counts
down by one byte every time a byte is transferred between
the DMA Controller and the Peripheral. When this register
reaches zero, the current buffer transfer is complete and
the TxTC/RxTC are generated and used to indicate this to
the peripheral. DMA transfers may also be stopped with
the TxEnd/RxEnd signals from the peripheral, where the
REMAIN register is non-zero at the end of transfer,
allowing software to determine the last valid data in a
buffer.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REMAIN