Cirrus Logic EP93xx - Manual (Page 503)

DS785UM1 13-7
Copyright 2007 Cirrus Logic
SDRAM, SyncROM, and SyncFLASH Controller
EP93xx User’s Guide
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Note: “RFU” means Reserved for Future Use.
Table 13-6 , Table 13-7 , and Table 13-8 show the bit field values for CASL, RAS, and Burst
Length, respectively.
When using a 32-bit wide external memory bus, the following Read addresses must be used
to set up the specified parameters, where H can be 0x0, 0xC, 0xD, 0xE or 0xF as shown in
Table 13-2 :
• SDRAM default READ Address: 0xH000_C800 — sets WBM=0, TM=0, CAS=3,
Sequential, BL=4
• SFLASH default READ Address: 0xH008_C800 — sets WBM=1, TM=0, CAS=3,
Sequential, BL=4
• SROM default READ Address: 0xH001_8400 — sets RAS=2, CAS=5, Sequential, BL=4
Table 13-6. Sync Memory CAS
CAS Value SDRAM SFLASH SROM
000 Reserved Reserved Reserved
001 Reserved 1 2
010 2 2 3
011 3 3 4
100 Reserved Reserved 5
101 Reserved Reserved 6
110 Reserved Reserved 7
111 Reserved Reserved 8
Table 13-7. Sync Memory RAS, Burst Type, and Write Burst Length
Value SDRAM SFLASH SROM
RAS = 0 Not applicable Not applicable 1 clk
RAS = 1 Not applicable Not applicable 2 clk
BT = 0 Sequential Sequential Sequential
BT = 1 Interleaved Interleaved Interleaved
WBM = 0 Use BL value Use BL value Use BL value
WBM = 1 Write Burst = 1 Write Burst = 1 Not applicable
Table 13-8. Burst Length
Burst Length SDRAM SFLASH SROM
000 Reserved 1 Reserved
001 Reserved 2 4
010 4 4 8
011 8 8 Reserved
100 Reserved Reserved ---
101 Reserved Reserved ---
110 Reserved Reserved ---
111 Reserved Reserved