Cirrus Logic EP93xx - Manual (Page 613)

DS785UM1 17-17
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
1
7
1
7
17
signalled. The CRC computation logic is preset to all ones before reception/transmission of
each frame and the result is inverted before it used for comparison or transmission. Note that
unlike the address, control and data fields, the 32 bit inverted CRC value is transmitted and
received from least significant byte to most significant and within each byte the least
significant nibble is encoded/decoded first. The cyclical redundancy checker uses the 32
term polynomial:
CRC(x) =
(x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1)
17.5.2 Functional Description
Following reset, the FIR is disabled. Reset also causes the transmit and receive buffers and
tail register to be flushed (buffers marked as empty). To transmit data in FIR mode, use the
following procedure:
1. Set the EN bits in the IrEnable register to 11b for FIR mode. Do not begin data
transmission.
2. Before enabling the FIR, the user must first clear any writable or “sticky” status bits that
are set by writing a one to each bit. (A sticky bit is a readable status bit that may be
cleared by writing a one to its location.) Set the TAB and TFC bits in the FISR register,
then read the FISR register to clear all interrupts.
3. Next, the desired mode of operation is programmed in the control register. Set the TXE
and RXE bits in the IrCtrl register.
4. Write 1 to 3 bytes to the appropriate IrDataTail register.
5. Once the FIR is enabled, transmission/reception of data can begin on the transmit and
receive pins.
17.5.2.1 Baud Rate Generation
The baud rate is derived by dividing down a fixed 48 MHz clock. The 8 MHz baud (time-slot)
clock for the receiver is synchronized with the 4 PPM data stream each time a transition is
detected on the receive data line using a digital PLL. To encode a 4.0 Mbps data stream, the
required “symbol” frequency is 2.0 MHz, with four chips per symbol at a frequency of
8.0 MHz. Receive data is sampled half way through each time-slot period by counting three
out of the six 48 MHz clock periods which make up each chip. Refer to
Figure 17-3 on
page 17-15 . The symbols are synchronized during preamble reception. Recall that the
preamble consists of four symbols repeated sixteen times. This repeating pattern is used to
identify the first time-slot or beginning of a symbol and resets the two bit chip counter logic,
such that the 4 PPM data is properly decoded.