Cirrus Logic EP93xx - Manual (Page 303)

DS785UM1 9-1
Copyright 2007 Cirrus Logic
9
9
9
Chapter 9
9 1/10/100 Mbps Ethernet LAN Controller
9.1 Introduction
The Ethernet LAN Controller incorporates all the logic needed to interface directly to the AHB
and to the Media Independent Interface (MII). It includes local memory and DMA control, and
supports full duplex operation with flow control support.
Figure 9-1 shows a simplified block
diagram.
This block was designed with a RAM of 544 words, each word containing 33 bits. These
RAMs are used for packet buffering and controller data storage. One RAM is dedicated to the
receiver, and one dedicated to the transmitter. These RAMs are mapped into the register
space and are accessible via the AHB.
Figure 9-1. 1/10/100 Mbps Ethernet LAN Controller Block Diagram
9.1.1 Detailed Description
9.1.1.1 Host Interface and Descriptor Processor
The Host Interface can be functionally decomposed into the AHB Interface Controller and the
Descriptor Processor. The AHB Interface Controller implements the actual connection to the
AHB. The controller responds as a AHB bus slave for register programming, and acts as an
AHB bus master for data transfers.
1/10/100
Mbit
Phy
1/10/100 MBPS Ethernet LAN Controller
(External)
MAC
TX/RX
Descriptor
Processors AHB
Reconciliation
Sub-layer
Interface
MII
AHB