Cirrus Logic EP93xx - Manual (Page 614)

17-18 DS785UM1
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
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17.5.2.2 Receive Operation
The IrDA standard specifies that all transmission occurs at half-duplex. This restriction forces
the user to enable one direction at a given time; either the transmit or receive logic, but not
both. However, the FIR’s hardware does not impose such a restriction. The user may enable
both the transmitter and receiver at the same time. Although forbidden by the IrDA standard,
this feature is particularly useful when using the FIR’s loop back mode, which internally
connects the output of the transmit serial shifter to the input of the receive serial shifter.
After the FIR is enabled for 4.0 Mbps transmission, the receiver logic begins by selecting an
arbitrary symbol boundary, receives four incoming 4 PPM symbols from the input pin using a
serial shifter and latches and decodes the symbols one at a time. If the symbols do not
decode to the correct preamble, the chip counter’s clock is forced to skip one 8MHz period,
effectively delaying the chip count by one. This process is repeated until the preamble is
recognized, signifying that the chip counter is synchronized. The preamble may be repeated
as few as sixteen times, or may be continuously repeated to indicate an idle receive line.
At any time after the transmission of sixteen preambles, the start flag may be received. The
start flag is eight symbols long. If any portion of the start flag does not match the standard
encoding, the receiver signals a framing error and the receive logic once again begins to look
for the frame preamble.
Once the correct start flag is recognized, each subsequent grouping of four DDs is decoded
into a data byte, placed within a five byte temporary buffer which is used to prevent the CRC
from being placed within the receive buffer. When the temporary buffer is filled, data values
are pushed out one by one to the receive buffer. The first data byte of a frame is the address.
If receiver address matching is enabled, the received address is compared to the address
programmed in the address match value field in one of the control registers. If the two values
are equal or if the incoming address contains all ones, all subsequent data bytes including
the address byte are stored in the receive buffer. If the values do not match, the receiver logic
does not store any data in the receive buffer, ignores the remainder of the frame and begins
to search for the next preamble. The second data byte of the frame can contain an optional
control field as defined by the user and must be decoded in software (there is no hardware
support within the FIR).
Frames can contain any amount of data in multiples of 8 bits up to a maximum of 2047 bytes
(including the address and control byte). In general this interface expects received frame size
to be limited to 2047 bytes. However, the interface can continue to operate past this limit, thus
it is the responsibility of the user to check that the size of each incoming frame does not
exceed the IrDA protocol’s maximum allowed frame size. The BC field in the IrRIB register
can not be used for this since it will over flow (and wrap), the true frame length can be
deduced from the DMA buffer position in combination with the BC field.
When the receive buffer contains a word of data, an interrupt or DMA request is signalled. If
the data is not removed soon enough and the buffer is completely filled, an overrun error is
generated when the receive logic attempts to place additional data into the full buffer. If this
occurs all subsequent data in the frame is discarded by the interface and the last valid entry
in the buffer is marked with the ROR and EOF bits. The interface will stall in this state until the
receiver buffer is emptied.