Cirrus Logic EP93xx - Manual (Page 238)

7-56 DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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ACRate
Address: 0x8003_0214
Default: 0x0000_0000
Definition: AC Toggle Rate register
Bit Descriptions:
RSVD: Reserved - Unknown during read
RATE: Rate - Read/Write
The RATE field must be written with a value that is one
less than the number of horizontal video lines before the
AC LCD bias signal is to toggle. Care must be taken when
choosing this value while using the grayscale dithering
algorithms, as a DC build-up may occur if the pixel timing
for the ‘on’ state of the pixel is concurrent with the bias
frequency.
FIFOLevel
Address: 0x8003_0234
Default: 0x0000_0010
Definition: FIFO Refill Level register
Bit Descriptions:
RSVD: Reserved - Unknown during read
LEVEL: Level - Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RATE
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD LEVEL