Cirrus Logic EP93xx - Manual (Page 402)

10-8 DS785UM1
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
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CE: Channel (Peripheral) Error
ICE: CONTROL[6] - Ignore Channel Error. This bit may be set
for data streams whereby the end user can tolerate
occasional bit errors. If it is not set then the DMA will abort
its transfer in receipt of a peripheral error.
ABORT: CONTROL[5]
10.1.9.1.1 DMA_IDLE
The DMA Channel FSM always resets to the DMA_IDLE state.
The DMA Channel FSM always enters the DMA_IDLE state when the channel is disabled
(CONTROL[4]).
10.1.9.1.2 DMA_STALL
The DMA Channel FSM enters the DMA_STALL state when the channel enabled, no STALL
interrupt is generated for this condition.
The DMA Channel FSM enters the DMA_STALL state if a memory buffer completes in the
ON state. A DMA_STALL interrupt is generated for this condition.
The DMA Channel FSM enters the DMA_STALL state and terminates the current memory
buffer if there is a peripheral error (TxEnd/RxEnd indication) while in the DMA_ON state, and
ICE is not active.
The DMA Channel FSM enters the DMA_STALL state and terminates the current memory
buffer if there is a peripheral error (TxEnd/RxEnd indication) while in the DMA_NEXT state,
and ABORT is active, and ICE inactive. No STALL interrupt is generated for this condition.
No data transfers occur in this state.
10.1.9.1.3 DMA_ON
The DMA Channel FSM enters this state when a base address is written in the stall state.
Data transfers occur in this state.
The DMA Channel FSM enters this state when the current memory buffer expires, or when a
peripheral error occurs that does not cause an abort, while in the DMA_NEXT state. The
transition from DMA_NEXT to DMA_ON state results in a NFB interrupt being generated.
10.1.9.1.4 DMA_NEXT
The DMA Channel FSM enters this state when a base address register is written in the
DMA_ON state (that is, for buffer Y). The DMA will continue to transfer using the buffer (that
is, buffer X) that it began with in the DMA_ON state. When buffer X expires or when a
peripheral error occurs, then the DMA will automatically switch over to using the next buffer
(buffer Y). It will generate an interrupt (NFBint) to signal to the processor that it is switching
over to a new buffer and that the old buffer descriptor (buffer X) is available to be updated.
Data transfers occur in this state.