Cirrus Logic EP93xx - Manual (Page 591)

DS785UM1 16-15
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
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6
1
6
16
CRCApd: CRC pass through.
0 - Do not pass received CRC to CPU.
1 - Pass received CRC to CPU.
IDLE: Idle mode.
0 - Idle-in Mark mode - When HDLC is idle (not
transmitting start or stop flags or packets), hold the
transmit data pin high.
1 - Idle-in Flag mode - When HDLC is idle, transmit
continuous flags.
AME: Address Match Enable. Activates address matching on
received frames.
00 - No address matching
01 - 4 x 1 byte matching
10 - 2 x 2 byte matching
11 - Undefined, no matching
RXE: HDLC Receive Enable.
0 - Disable HDLC RX. If UART is still enabled, UART may
still receive normally.
1 - Enable HDLC RX.
TXE: HDLC Transmit Enable.
0 - Disable HDLC TX. If UART is still enabled, UART may
still transmit normally.
1 - Enable HDLC TX.
TUS: Transmit FIFO Underrun Select
0 - TX FIFO underrun causes CRC (if enabled) and stop
flag to be transmitted.
1 - TX FIFO underrun causes abort (escape-flag) to be
transmitted.
CRCE: CRC enable.
0 - No CRC generated by HDLC TX or expected by HDLC
RX.
1 - HDLC TX automatically generates and sends a CRC at
the end of a packet, and HDLC RX expects a CRC at the
end of a packet.
CRCS: CRC size.
0 - CRC-16: x
16
+ x
12
+ x
5
+ 1
1 - CRC-32: x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+
x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1