Cirrus Logic EP93xx User Manual
Page 724
23-12
DS785UM1
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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Figure 23-10. Microwire Frame Format (Continuous Transfers)
23.5.11.1 Setup and Hold Time Requirements on SFRMIN with
Respect to SCLKIN in Microwire Mode
In the Microwire mode, the SSP slave samples the first bit of receive data on the rising edge
of SCLKIN after SFRMIN has gone LOW. Masters that drive a free-running SCLKIN must
ensure that the SFRMIN signal has sufficient setup and hold margins with respect to the
rising edge of SCLKIN.
illustrates these setup and hold time requirements. With respect to the SCLKIN
rising edge on which the first bit of receive data is to be sampled by the SSP slave, SFRMIN
must have a setup of at least two times the period of SCLKIN on which the SSP operates.
With respect to the SCLKIN rising edge previous to this edge, SFRMIN must have a hold of
at least one SCLKIN period.
Figure 23-11. Microwire Frame Format, SFRMIN Input Setup and Hold Requirements
LSB
0
MSB
MSB
LSB
LSB
MSB
4 to 16 bits output data
8-bit control
SCLK
SFRM
SSPTXD
SSPRXD
S C L K IN
S F R M IN
S S P R X D
F irs t R X d a ta b it to b e
s a m p le d b y S S P s la v e
0
M S B
t
c lk m ax
t
s e tu p
= (2 t
S S P C L K IN
)
t
h o ld
= t
S S P C L K IN