Cirrus Logic EP93xx - Manual (Page 792)

28-2 DS785UM1
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
2
8
2
8
28
Figure 28-1. System Level GPIO Connectivity
Port A
EGPIO[7:0]
MUX_IO OE
DATA
EP
Control
Mux
Controls
Port B
EGPIO[15:8]
MUX_IO OE
DATA
EP
Control
Mux
Controls
Port C
ROW[7:0]
MUX_IO OE
DATA
EP
Control
Mux
Controls
Port D
COL[7:0]
MUX_IO OE
DATA
EP
Control
Mux
Controls
Port E MUX_IO OE
DATA
EP
Control
Mux
Controls
Port F
VS2
MUX_IO OE
DATA
EP
Control
Mux
Controls
Port G
DD[15:12]
MUX_IO OE
DATA
EP
Control
Mux
Controls
Port H
DD[7:0]
MUX_IO OE
DATA
EP
Control
Mux
Controls
SLA[1:0]
EEDAT
EECLK
IDEDA[2:0]
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
IDECS0n
IDECS1n
DIORn
RDLED
GRLED
READY
VS1
MCBVD2
MCBVD1
MCCD2
MCCD1
WP