Vactivestrtstop – Cirrus Logic EP93xx User Manual
Page 221
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Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
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When the Vertical counter counts down to the written
STOP value, the VSYNC signal on the V_CSYNC pin will
go inactive if CSYNC = ‘0’ and SYNCEN = ‘1’ in the
register. Please refer to the video signalling
timing diagrams shown in
.
STRT: Start
-
Read/Write
When the Vertical counter counts down to the written
STRT value, the VSYNC signal on the V_CSYNC pin will
go active if CSYNC = ‘0’ and SYNCEN = ‘1’ in the
register.
VActiveStrtStop
Address: 0x8003_0008
Default: 0x0000_0000
Definition: Vertical Active Start/Stop register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
STOP:
Stop - Read/Write
The STOP value is the value of the Vertical down counter
at which the VACTIVE signal becomes inactive (stops).
This indicates the end of the active video portion for the
Vertical frame. Please refer to the video signalling timing
diagrams in
. VACTIVE is an
internal block signal. The active video interval is controlled
by the logical OR of VACTIVE and HACTIVE.
STRT:
Start - Read/Write
The STRT value is the value of the Vertical down counter
at which the VACTIVE signal becomes active (starts). This
indicates the start of the active video portion for the
Vertical frame. Please refer to the video signalling timing
diagrams in
. VACTIVE is an
internal block signal. The active video interval is controlled
by the logical OR of VACTIVE and HACTIVE.
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30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
STOP
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
STRT