Cirrus Logic EP93xx - Manual (Page 782)

27-12 DS785UM1
Copyright 2007 Cirrus Logic
IDE Interface
EP93xx User’s Guide
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Note: At most, one of the above 3 bits should be set to 1 at any time. If more than one is set, the
results will be unpredictable, and the data invalid.
MODE: Speed mode number. (0 to 4 defined for PIO, 0 to 2
defined for MDMA, 0 to 4 defined for UDMA).
WST: Wait State for Turn. Number of HCLK cycles to hold the
data bus after a PIO write operation.
IDEMDMAOp
Address:
0x800A_0008 Read/Write
Default:
0x0000_0000
Definition:
IDE MDMA Configuration Register.
Bit Descriptions:
RSVD: Reserved. Unknown during read, ignored during write.
MEN: Enable Multiword DMA operation.
1 - to start MDMA
0 - to terminate MDMA by the host.
RWOP: Read or write operation selection:
0 - Read
1 - Write.
IDEUDMAOp
Address:
0x800A_000C - Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RWOP MEN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RWOP UEN