Cirrus Logic EP93xx - Manual (Page 138)

5-12 DS785UM1
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
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set. One example of this is when a power-on-reset is applied and this register bit is cleared.
This means that this bit will not be set on boot-up and will have to be set to maintain the
memory image for when the device re-enters Standby mode.
5.1.6.2.3 RUN HALT mode
A transition from Run mode to Halt mode is caused by reading the Halt register location
0x8093_0008 with the SHena bit set to 1. This has the effect of gating the CPU clock (FCLK)
bus interface, with the APB/AHB system clock, and Memory/DMA system remaining enabled.
5.1.6.2.4 STANDBY RUN mode
There are normally several conditions in which the device can move from Standby mode to
Run mode.
These conditions are:
• A falling edge on IRQ interrupt
• A falling edge on FIQ interrupt
• An exit from a "ClkSet1" write
• PRSTn
• RSTOn
The EP93xx comes out of Standby if an interrupt occurs or when an exit from a ClkSet1 write
occurs. If a write is performed to the ClkSet1 register, the EP93xx then enters Standby mode
and then automatically comes out of Standby mode and back into the Run state.
5.1.6.2.5 HALT RUN mode
The transition from the Halt state to the Run state is caused by:
• A falling edge on IRQ interrupt
• A falling edge on FIQ interrupt
• RSTOn
5.1.7 Interrupt Generation
The Syscon block generates two interrupts: TICK interrupt and Watchdog Expired interrupt.
The block generates the TICK interrupt based upon the 64 Hz clock, which is derived from
the 32.768 KHz oscillator. The interrupt becomes active on every rising edge of the internal
64 Hz clock. It can be cleared by writing to the TEOI location.
Watchdog Expired interrupt becomes active on a rising edge of the 64 Hz TICK clock, if the
TICK interrupt is still active. In other words, if a TICK interrupt has not been served for a
complete TICK period, a watchdog expired interrupt is generated. It can be cleared by writing
to the TEOI location as well.