Cirrus Logic EP93xx - Manual (Page 64)

2-26 DS785UM1
Copyright 2007 Cirrus Logic
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2
2
2
0x8082_003C I2STX2En TX2 Channel Enable N
0x8082_0040 I2SRX0Lft Left Receive data Register for channel 0 N
0x8082_0044 I2SRX0Rt Right Receive data Register for channel 0 N
0x8082_0048 I2SRX1Lft Left Receive data Register for channel 1 N
0x8082_004C I2SRX1Rt Right Receive data Register for channel 1 N
0x8082_0050 I2SRX2Lft Left Receive data Register for channel 2 N
0x8082_0054 I2SRX2Rt Right Receive data Register for channel 2 N
0x8082_0058 I2SRXLinCtrlData Receive Line Control Register N
0x8082_005C I2SRXCtrl Receive Control Register N
0x8082_0060 I2SRXWrdLen Receive Word Length N
0x8082_0064 I2SRX0En RX0 Channel Enable N
0x8082_0068 I2SRX1En RX1 Channel Enable N
0x8082_006C I2SRX2En RX2 Channel Enable N
0x8083_xxxx SECURITY Security Registers
0x8083_2714 ExtensionID Contains the Part ID for EP93XX devices N
Contact Cirrus Logic for details regarding implementation of device Security measures.
0x8084_xxxx GPIO GPIO Control Registers
0x8084_0000 PADR GPIO Port A Data Register N
0x8084_0004 PBDR GPIO Port B Data Register N
0x8084_0008 PCDR GPIO Port C Data Register N
0x8084_000C PDDR GPIO Port D Data Register N
0x8084_0010 PADDR GPIO Port A Data Direction Register N
0x8084_0014 PBDDR GPIO Port B Data Direction Register N
0x8084_0018 PCDDR GPIO Port C Data Direction Register N
0x8084_001C PDDDR GPIO Port D Data Direction Register N
0x8084_0020 PEDR GPIO Port E Data Register N
0x8084_0024 PEDDR GPIO Port E Data Direction Register N
0x8084_0028 - 0x8084_002C Reserved
0x8084_0030 PFDR GPIO Port F Data Register N
0x8084_0034 PFDDR GPIO Port F Data Direction Register N
0x8084_0038 PGDR GPIO Port G Data Register N
0x8084_003C PGDDR GPIO Port G Data Direction Register N
0x8084_0040 PHDR GPIO Port H Data Register N
0x8084_0044 PHDDR GPIO Port H Data Direction Register N
0x8084_0048 Reserved
0x8084_004C GPIOFIntType1
Register controlling type, level or edge, of interrupt generated by
the pins of Port F
N
0x8084_0050 GPIOFIntType2
Register controlling polarity, high/low or rising/falling, of interrupt
generated by Port F
N
0x8084_0054 GPIOFEOI GPIO Port F End Of Interrupt Register N
0x8084_0058 GPIOFIntEn Interrupt Enable for Port F N
Table 2-8. Internal Register Map (Continued)
Address Register Name Register Description
SW
Lock