Cirrus Logic EP93xx - Manual (Page 643)

DS785UM1 19-1
Copyright 2007 Cirrus Logic
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Chapter 19
19 Watchdog Timer
19.1 Introduction
The Watchdog Timer provides a mechanism for generating a system-wide reset should the
system hang. This functionality allows the Watchdog to recover the system and report the
recovery to software. To prevent system-wide reset, software must periodically reset the
Watchdog via an APB write operation. It is possible to disable the Watchdog through either
hardware or software.
The Watchdog timer circuitry consists of a 7-bit counter. The most significant bit of the
counter is used to trigger the WATCHDOG_RESETn output signal to the system control
module for generating HRESETn.
The amount of time before a WATCHDOG_RESETn is initiated as well as the duration of the
reset pulse is as follows:
• Time-out or WATCHDOG_RESETn duration = 64 / WATCHDOG_CLK frequency (units
are seconds).
• For a 256 Hz WATCHDOG_CLK, time-out and reset pulse duration are
64 / 256 = 250 msec.
To keep the reset pulse from occurring, SW must reset the Watchdog timer (sometimes
known as “kick the dog”) to a predetermined count on a periodic basis. This resets the
counter, which prevents the WATCH_RESETn from activating. The counter is reset by writing
0x5555 to the Watchdog register. The Watchdog should be reset at least 2
WATCHDOG_CLK periods earlier than the time-out calculation would indicate, due to clock
synchronization and handshaking circuitry.
Once a Watchdog reset occurs, the timer also provides a 250 ms duration reset pulse. The
Watchdog also defaults to providing the pulse duration when the reset is from other sources
such as user reset (external reset on RSTOn), AMBA bus reset (HRESETn), or power on
reset (internal chip voltage detect power on signal PWR_RESETn). The reset pulse duration
can be disabled by pulling the CSn[2] (HW_RSTPULSE_DISABLEn) signal low during the
bus reset (HRESETn low). This immediately frees the Watchdog reset output line when reset
becomes inactive. In either case, if the reset pulse duration is provided or not, the Watchdog
counter will start over after the WATCHDOG_RESETn output becomes inactive. This begins
a new 250 ms cycle after reset becomes inactive before software must reset the counter.