Cirrus Logic EP93xx - Manual (Page 272)

8-8 DS785UM1
Copyright 2007 Cirrus Logic
Graphics Accelerator
EP93xx User’s Guide
8
8
8
8.4.6 Memory Map Access
The Graphics Accelerator has access to the entire memory map. Therefore pixel block
function processing is not limited to graphics and video memory. Font storage, bit map
storage, etc. can be stored anywhere in the memory map. To alleviate page miss penalties
for copies between SDRAM memory pages, the Graphics Accelerator uses a 32-entry copy
buffer during block transfers.
8.5 Register Programming
Some of the registers used to operate the Graphics Accelerator need extra explanation for
proper usage. There are two sets such registers. They specify Word Count and Pixel
End/Start values.
8.5.1 Word Count
The “BLKSRCWIDTH” and “BLKDESTWIDTH” registers must be written with the ‘number of
32-bit words minus 1’ that are to be fetched from the SDRAM buffer. If any pixel bit is in a
word. it must be counted as a full word.
8.5.1.1 Example: 8 BPP mode
If a Block Copy starts at pixel 0 and 7 pixels are to be copied, the “BLKSRCWIDTH” register
would be loaded with a 0x1 (2 words - 1 word = 0x1) since the 7th pixel resides in word 1 and
the 0th pixel resides in word 0. The pixels fetched are highlighted in
Table 8-8 .
If a Block Copy starts at pixel 0 and 2 pixels are to be copied, the “BLKSRCWIDTH” register
would be loaded with 0x0 (1 word - 1 word = 0x0). The pixels fetched are highlighted in
Table 8-9 .
0x00B0 unused P(4,5)R P(4,5)G P(4,5)B
0x00B4 unused P(5,5)R P(5,5)G P(5,5)B
0x00B8 unused P(6,5)R P(6,5)G P(6,5)B
0x00BC unused P(7,5)R P(7,5)G P(7,5)B
Table 8-8. Transfer Example 1
Address 31 0 31 0 31 0 31 0
0x0000 -
0x000C
FF EE DD CC BB AA 99 88 77 66 55 44 33 22 11 00
Table 8-7. 24 bpp Unpacked Memory Organization (1 pixel/ 1 word)