Cirrus Logic EP93xx - Manual (Page 375)

DS785UM1 9-73
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Definition:
Receive Descriptor Queue Current Length register. The Receive Descriptor
Queue Current Length defines the number of bytes between the Receive
Descriptor Current Address and the end of the receive descriptor queue. This
value is used internally to wrap the pointer back to the start of the queue. The
register should not normally be written.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RDCL: Receive Descriptor Current Length.
RXDCurAdd
Address:
0x8001_0098 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Descriptor Current Address register. The Receive Current Descriptor
Address contains the pointer to the next entry to be read from the receive
descriptor queue. This should be set at initialization time to the required
starting point in the descriptor queue. During operation the MAC will update
this address following successful descriptor reads. Intermediate values in this
register will not necessarily align to descriptor boundaries, nor directly effect
the current descriptor in use because several descriptors may be buffered
inside the MAC.
Bit Descriptions:
RDCA: Receive Descriptor Current Address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDCA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDCA