Cirrus Logic EP93xx - Manual (Page 133)

DS785UM1 5-7
Copyright 2007 Cirrus Logic
System Controller
EP93xx User’s Guide
5
5
5
Figure 5-3. Bus Clock Generation
There are some limitations of each clock. FCLK must be <=200 MHz, HCLK<=100 MHz and
PCLK<=50 MHz and FCLK >= HCLK > PCLK. Refer to register,
“ClkSet1” on page 5-18 , for
the detailed configuration information regarding the divider bit fields.
HCLK
Div
FCLK
Div
PLL1 External Clock
PCLK
Div
FCLK
HCLK
PCLK
FCLK Divide = 1, 2, 4, 8, 16
HCLK Divide = 1, 2, 4, 5, 6,
For 2nd stage dividers:
PCLK Divide = 1, 2, 4, 8
MAX = 100 MHz
MAX = 250 MHz
MAX = 500 MHz
MAX = 50 MHz
8, 16, 32