Cirrus Logic EP93xx - Manual (Page 655)

DS785UM1 20-7
Copyright 2007 Cirrus Logic
Real Time Clock With Software Trim
EP93xx User’s Guide
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RTCSWComp
Address:
0x8092_0108 - Read/Write
Default:
0x0000_7FFF
Mask:
003F_FFFF
Definition:
RTC Software Compensation Register.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
0: Must be written as “0”.
DEL: Number of clocks to delete. This value determines the
number of 32.768 KHZ clocks to delete every 32 seconds
for compensating the oscillator. The value defaults to 0x0
which deletes no clock pulses.
INT: Counter pre-load Integer value. This value is pre-loaded
into the counter as the integer divide portion of the
oscillator compensation. If set to 0x0000, no integer divide
occurs and no clock pulses are deleted. The value defaults
to 0x7FFF which causes the divider to divide by exactly
32,768 to generate a 1 Hz clock.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD 0 DEL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INT