Cirrus Logic EP93xx - Manual (Page 73)

DS785UM1 3-3
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
• Inexact
Note that the division by zero exception is not supported as the MaverickCrunch co-
processor does not provide division or square root.
3.1.3 Pipelines and Latency
There are two primary pipelines within the MaverickCrunch co-processor. One handles all
communication with the ARM920T, while the other, the “data path” pipeline, handles all
arithmetic operations (this one actually operates at one half the MaverickCrunch co-
processor clock frequency).
The data path pipeline may run synchronously or asynchronously with respect to the ARM
instruction pipeline. If run asynchronously, data path computation is decoupled from the ARM,
allowing high throughput, though arithmetic exceptions are not synchronous. If run
synchronously, exceptions are synchronous, but throughput suffers.
Assuming no inter-instruction dependencies causing pipeline stalls, arithmetic instructions
can produce a new result every two ARM920T clocks, which is a maximum throughput of one
data path instruction per eight ARM920T clocks. The only exception is 64-bit multiplies
(CFMULD or CFMUL64), which require six extra ARM920T clocks to produce their result,
which is maximum throughput of eight ARM920T clocks per instruction.
The normal latency for an arithmetic instruction is approximately nine ARM920T clocks, from
initial decode to the time the result is written to the register file. A 64-bit multiply requires 15
clocks.
3.1.4 Data Registers
The MaverickCrunch co-processor contains these registers:
• Sixteen 64-bit general purpose registers, c0 through c15
• Four 72-bit accumulators, a0 through a3
• One status and control register, DSPSC
A single precision floating point value is stored in the upper 32 bits of a 64-bit register and
must be explicitly promoted to double precision to be used in double precision calculations:
Opcode
63 62 55 32 31 0
Sign Exponent Significand not used