Cirrus Logic EP93xx - Manual (Page 798)

28-8 DS785UM1
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
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1. IDEDA[2:0], IDECS0n, IDECS1n, and DIORn are IDE control pins.
2. VS2, VS1, MCBVD[2:1], MCD[2;1], READY, and WP are PCMCIA pins.
3. SLA[1:0] are the PCMCIA voltage control pins.
4. DD[15:0] are the IDE data pins. DD[11:8] has no GPIO pin mapping.
5. GRLED is the Green LED pin.
6. RDLED is the Red LED pin.
7. EECLK is the EEPROM clock pin.
8. EEDAT is the EEPROM data pin.
9. ROW[7:0] are the Key Matrix row pins.
Table 28-4. EP9315 GPIO Port to Pin Map
Pin
Name
Default
Function
Function in
GonK
Mode
Function in
EonIDE
Mode
Function in
GonIDE
Mode
Function in
HonIDE
Mode
EGPIO[7:0] Port A Port A Port A Port A Port A
EGPIO[15:8] Port B Port B Port B Port B Port B
GRLED 5 Port E0 Port E0 Port E0 Port E0 Port E0
RDLED 6 Port E1 Port E1 Port E1 Port E1 Port E1
VS2
2 Port F7 Port F7 Port F7 Port F7 Port F7
READY 2 Port F6 Port F6 Port F6 Port F6 Port F6
VS1 2 Port F5 Port F5 Port F5 Port F5 Port F5
MCBVD[2:1] 2 Port F4:3 Port F4:3 Port F4:3 Port F4:3 Port F4:3
MCD[2:1]
2 Port F2:1 Port F2:1 Port F2:1 Port F2:1 Port F2:1
WP 2 Port F0 Port F0 Port F0 Port F0 Port F0
EECLK 7 Port G0 Port G0 Port G0 Port G0 Port G0
EEDAT 8 Port G1 Port G1 Port G1 Port G1 Port G1
SLA[1:0]
3 Port G3:2 Port G3:2 Port G3:2 Port G3:2 Port G3:2
ROW[7:0] 9 ROW[7:0] Port C ROW[7:0] ROW[7:0] ROW[7:0]
COL[7:0] 10 COL[7:0] Port D COL[7:0] COL[7:0] COL[7:0]
IDEDA[2:0] 1 IDEDA[2:0] IDEDA[2:0] Port E7:5 IDEDA[2:0] IDEDA[2:0]
IDECS1n 1 IDECS1n IDECS1n Port E4 IDECS1n IDECS1n
IDECS0n 1 IDECS0n IDECS0n Port E3 IDECS0n IDECS0n
DIORn 1 DIORn DIORn Port E2 DIORn DIORn
DD[15:12]
4 DD[15:12] DD[15:12] DD[15:12] Port G7:4 DD[15:12]
DD[11:8] 4 DD[11:8 DD[11:8] DD[11:8] DD[11:8] DD[11:8]
DD[7:0] DD[7:0] DD[7:0] DD[7:0] DD[7:0] Port H