Cirrus Logic EP93xx - Manual (Page 687)

DS785UM1 21-31
Copyright 2007 Cirrus Logic
I 2 S Controller
EP93xx User’s Guide
2
1
2
1
21
rx2_fifo_empty: when = 1, FIFO is empty, otherwise not empty
rx2_fifo_half_full: when = 1, FIFO is half full, otherwise less than half full
I2SGlCtrl
Address:
0x8082_000C - Read/Write
Default:
0x0000_0000
Definition:
I
2
S Global Control Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
i2s_ife: Defines if I
2
S controller is enabled and PCLK is turned on
for the I
2
S controller.
0 - PCLK is off.
1 - PCLK is on.
i2s_loopback: Defines loopback operation.
0 - not in loopback mode
1 - Loopback mode selected.
The I
2
S global register deals with enabling the block and whether loopback mode is used.
The I
2
S enable bit determines whether the PCLK is turned on for the I
2
S. All registers except
for the data registers can be written without the I
2
S PCLK enabled. The ARM provides its own
clock cycles when writing to any of the control status registers.
When the I
2
S controller is required to transmit or receive data, PCLK must be turned on via
this register.
The I
2
S controller loopback mode bit determines if TX channel 0 is connected to RX channel
0. This will allow data be sent in a loop fashion from the transmitter back through the receiver.
This applies to all channels, with TX1 looped to RX1, and TX2 looped to RX2. When
loopback is active, data at the receiver input is ignored and transmit data is sent out normally.
The transmit section will control the clock configuration during loopback the same as if full-
duplex operation was used.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD i2s_loopback i2s_ife