Srcpixelstrt, Destpixelstrt, Regi – Cirrus Logic EP93xx User Manual
Page 287: Register descriptions
DS785UM1
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Copyright 2007 Cirrus Logic
Graphics Accelerator
EP93xx User’s Guide
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Register Descriptions
SRCPIXELSTRT
Address:
0x8004_0000 - Read/Write
Default:
0x0000_0000
Mask:
0x0000_001F
Definition:
Source Pixel Start register
Bit Descriptions:
RSVD:
Reserved - Unknown during read
PEL:
Source Pixel Location - Read/Write
For the starting pixel (at the starting X-Y coordinate of the
1st scan line) of the source image for a block copy, the
value in this field specifies where the beginning bit of the
pixel is located in a 32-bit word. For example, if the
beginning bit of a 16-bit pixel is located at bit 16 of a 32-bit
word, PEL = 0x10.
The PEL field and the ADR field in the
register together define the starting pixel’s address in the
SDRAM frame buffer. In REMAP mode, the starting
location written to the PEL field can be defined with bit-
level granularity. For all other modes, the granularity must
be a multiple of the pixel size: e.g. in 8 bpp mode,
acceptable PEL values are 0x00, 0x08, 0x10, and 0x18.
DESTPIXELSTRT
Address:
0x8004_0004 - Read/Write
31
30
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28
27
26
25
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23
22
21
20
19
18
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16
RSVD
15
14
13
12
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10
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2
1
0
RSVD
PEL
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
EPEL
15
14
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12
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10
9
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5
4
3
2
1
0
RSVD
SPEL