Cirrus Logic EP93xx User Manual
Page 802
28-12
DS785UM1
Copyright 2007 Cirrus Logic
GPIO Interface
EP93xx User’s Guide
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8
2
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PxDIR:
Port x direction bits.
GPIOxIntEn
Address:
GPIOAIntEn: 0x8084_009C - Read/Write
GPIOBIntEn: 0x8084_00B8 - Read/Write
GPIOFIntEn: 0x8084_0058 - Read/Write
Definition:
The GPIO Interrupt Enable register controls which bits of port A/B/F are to be configured as
interrupts. A “1” written to a bit in this register will configure the bit on port A/B/F to become an
interrupt. The user must make sure that the direction of port A/B/F is set to input (PxDDR
defaults to input on reset). Writing a “0” (default on reset) to a bit in the register will configure
that bit on port A/B/F as a normal GPIO port and the interrupt output corresponding to that bit
will be zeroed. The user can read the inputs on port A/B/F in either mode via the PxDR.
The interrupt type is controlled by the GPIOxINTTYPE1/2 registers described in the following
sections.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
PxINT:
Port x interrupt enables.
GPIOxIntType1
Address:
GPIOAIntType1: 0x8084_0090 - Read/Write
GPIOBIntType1: 0x8084_00AC - Read/Write
GPIOFIntType1: 0x8084_004C - Read/Write
Definition:
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
PxINT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
PxINTE