Cirrus Logic EP93xx User Manual

Page 371

DS785UM1

9-69

1/10/100 Mbps Ethernet LAN Controller

EP93xx User’s Guide

TxEn:

Transmit Enable. Writing a one to Transmit Enable causes
transmit DMA transfers to be enabled. This is reflected in
TxAct (Bus Master Status) being set. TxEn is an act-once-
bit and will clear automatically when the enable is
complete. The first time the TxEn bit is set following an
AHB reset, or a TxChRes, the MAC performs a transmit
channel initialization. During this initialization the TXDEnq
is cleared, and the Transmit Descriptor and Status Queues
are calculated. When the initialization is complete, the
TxAct (BMSts) is set.

EH2:

Enable Header 2. When Enable Header2 is set, a status is
written to the receive status queue when the number of
bytes specified in Receive Header Length2 have been
transferred to the receive data buffer. If the transfer either
fills a receive buffer or ends a receive frame, only an end
of buffer or end of frame status is generated. The value in
Receive Header Length 2 should be greater than the value
in Receive Header Length 1 in order to generate a status
event.

EH1:

Enable Header 1. When Enable Header1 is set, a status is
written to the receive status queue when the number of
bytes specified in Receive Header Length1 have been
transferred to the receive data buffer. If the transfer either
fills a receive buffer or ends a receive frame, only an end
of buffer or end of frame status is generated.

EEOB:

Enable EOB. When Enable End Of Buffer bit is set, a
status is written to the receive status queue whenever an
end of receive buffer is reached. If reaching the end of the
receive buffer coincides with the end of frame, only one
status is written to the queue.

RxChR:

Receive Channel Reset. Writing a “1” to Receive Channel
Reset causes the Receive Descriptor Processor and the
receive FIFO to be reset. This bit is an act-once-bit and
will clear automatically when the reset is complete.

RxDis:

Receive Disable. Writing a “1” to Receive Disable causes
receive DMA transfers to be halted. If a receive frame is
currently in progress, transfers will be halted when the
receive frame status has been transferred to the status
buffer. When the transfers are halted, the RxAct bit (Bus
Master Status) is cleared. This bit is an act-once-bit and
will clear immediately.