Cirrus Logic EP93xx User Manual
Page 236
7-54
DS785UM1
Copyright 2007 Cirrus Logic
Raster Engine With Analog/LCD Integrated Timing and Interface
EP93xx User’s Guide
7
7
7
1 - Pixel data output changes on falling edge of the clock
on the SPCLK pin
BLKPOL:
Blank Polarity - Read/Write
The value written to this bit selects the polarity of the
blanking signal on the BLANK pin:
0 - BLANK is active LOW (default)
1 - BLANK is active HIGH
HSPOL:
Horizontal Sync Polarity - Read/Write
The value written to this bit selects the polarity of the
horizontal synchronization signal on the HSYNC pin:
0 - HSYNC is active LOW (default)
1 - HSYNC is active HIGH
V/CPOL:
Vertical / Composite Polarity - Read/Write
The value written to this bit selects the polarity of the
synchronization signal on the V_CSYNC pin:
0 - V_CSYNC is active LOW (default)
1 - V_CSYNC is active HIGH
CSYNC:
Composite Sync - Read/Write
The value written to this bit selects whether the Vertical
Sync or the Composite Sync signal is routed to the
V_CSYNC pin:
0 - Vertical Sync
1 - Composite Sync
DATEN:
Pixel Data Enable - Read/Write
The value written to this bit selects whether pixel data is
output to the P[x] pins, or not:
0 - Pixel data output disabled
1 - Pixel data output enabled
SYNCEN:
Video Sync Enable - Read/Write
The value written to this bit selects whether
synchronization signals are output to the H_SYNC and
V_CSYNC pins, or not:
0 - Video SYNC outputs disabled
1 - Video SYNC outputs enabled