Cirrus Logic EP93xx - Manual (Page 369)

DS785UM1 9-67
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Soft Reset:
0x0000_0000
Definition:
MII Status Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
Busy: MII Busy. The Busy bit is set whenever a command is
written to the MII Command Register. It is cleared when
the operation has been completed.
Descriptor Processor Registers
The Descriptor Processor Registers are in three parts: the bus master control, receive
registers, and transmit registers.
BMCtl
Address:
0x8001_0080 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
0x0000_0000
Definition:
Bus Master Control Register
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD MT TT UnH TxChR TxDis TxEn RSVD EH2 EH1 EEOB RSVD RxChR RxDis RxEn