Cirrus Logic EP93xx - Manual (Page 559)

DS785UM1 15-1
Copyright 2007 Cirrus Logic
1
5
1
5
15
Chapter 15
15 UART2
15.1 Introduction
UART2 implements a UART interface identical to that of UART1. UART2 does not implement
a modem or HDLC interface. For additional details about UART1, refer to
Chapter 14 ,
“UART1 With HDLC and Modem Control Signals” on page 14-1 .
UART2 and the IrDA blocks cooperatively implement a Slow Infrared (SIR) interface. The
register interface for each block is separate. The UART2 control registers are at base
address 0x808D_0000 and the IrDA controller registers are at base address 0x808B_0000.
For additional details about IrDA, refer to
Chapter 17 , “IrDA” on page 17-1 . The UART SIR
interface is described below.
15.2 IrDA SIR Block
The IrDA SIR block contains an IrDA SIR protocol Encoder/decoder. The SIR protocol
Encoder/decoder can be enabled for serial communication via signals nSIROUT and SIRIN
to an infrared transducer instead of using the UART signals UARTTXD and UARTRXD.
If the SIR protocol Encoder/decoder is enabled, the UARTTXD line is held in the passive
state (HIGH) and transitions of the modem status or the UARTRXD line will have no effect.
The SIR protocol Encoder/decoder can both receive and transmit, but it is half-duplex only, so
it cannot receive while transmitting, or vice versa.
The IrDA SIR physical layer specifies a minimum 10 ms delay between transmission and
reception.
15.2.1 IrDA SIR Encoder/decoder Functional Description
The IrDA SIR Encoder/decoder comprises:
• IrDA SIR transmit encoder
• IrDA SIR receive decoder
This is shown in Figure 15-1 :