Txdqblen, Txdqcurlen, Tdba: transmit descriptor base address – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
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Bit Descriptions:
TDBA:
Transmit Descriptor Base Address.
TXDQBLen
Address:
0x8001_00B4 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Transmit Descriptor Queue Base Length register. The Transmit Descriptor
Queue Base Length defines the actual number of bytes in the transmit
descriptor queue, which thereby sets the maximum number of transmit
descriptors that can be supplied to the MAC at any one time. The length
should be set at initialization time and must define an integral number of
transmit descriptors.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
TDBL:
Transmit Descriptor Base Length.
TXDQCurLen
Address:
0x8001_00B6 - Read/Write. Note half word alignment.
Chip Reset:
0x0000_0000
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RSVD
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1
0
TDBL
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RSVD
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1
0
TDCL