Cirrus Logic EP93xx - Manual (Page 594)

16-18 DS785UM1
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
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UART3HDLCSts
Address:
0x808E_021C - Read/Write
Default:
0x0000_0000
Definition:
HDLC Status Register. The TFS and RFS bits in this register are replicas of
bits in the UART3 status register.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
CRE: CRC Error. (Read Only)
0 - No CRC check errors encountered in incoming frame.
1 - CRC calculated on the incoming data does not match
CRC value contained within the received frame. This bit is
set with the last data in the incoming frame along with
EOF.
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
changes with reads from the RX FIFO.
ROR: Receive FIFO Overrun. (Read Only)
0 - RX FIFO has not overrun.
1 - RX logic attempted to place data in the RX FIFO while
it was full. The most recently read data is the last valid
data before the overrun. The rest of the incoming frame is
dropped. EOF is also set.
Note: This bit reflects the status associated with the last character read from the RX FIFO. It
changes with reads from the RX FIFO.
TBY: Transmitter Busy. (Read Only)
0 - TX is idle, disabled, or transmitting an abort.
1 - TX is currently sending a frame (address, control, data,
CRC or start/stop flag).
RIF: Receiver In Frame. (Read Only)
0 - RX is idle, disabled or receiving start flags
1 - RX is receiving a frame.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD CRE ROR TBY RIF RSVD RAB RTO EOF RFL RIL RFC RFS TAB TFC TFS