Cirrus Logic EP93xx - Manual (Page 552)

14-30 DS785UM1
Copyright 2007 Cirrus Logic
UART1 With HDLC and Modem Control Signals
EP93xx User’s Guide
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4
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14
CRCZ: CRC zero seed
0 - Seed CRC calculations with all ones; that is, 0xFFFF
for 16 bit words and 0xFFFF_FFFF for 32 bit words.
1 - Seed CRC calculations with all zeros.
Applies to both RX and TX.
RXE: HDLC Receive Enable.
0 - Disable HDLC RX. If UART is still enabled, UART may
still receive normally.
1 - Enable HDLC RX.
TXE: HDLC Transmit Enable.
0 - Disable HDLC TX. If UART is still enabled, UART may
still transmit normally.
1 - Enable HDLC TX.
TUS: Transmit FIFO Underrun Select
0 - TX FIFO underrun causes CRC (if enabled) and stop
flag to be transmitted.
1 - TX FIFO underrun causes abort (escape-flag) to be
transmitted.
CRCE: CRC enable.
0 - No CRC is generated by TX or expected by RX.
1 - HDLC TX automatically generates and sends a CRC at
the end of a packet, and HDLC RX expects a CRC at the
end of a packet.
CRCS: CRC size.
0 - CRC-CCITT (16 bits): x
16
+ x
12
+ x
5
+ 1
1 - CRC-32: x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+
x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1
If inverted (see CRCN bit) the CRC-16 check value is
0x1D0F and the CRC-32 check value is 0xC704_DD7B.
Otherwise the check value is zero.
UART1HDLCAddMtchVal
Address:
0x808C_0210 - Read/Write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
AMV
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AMV