Vicxdefvectaddr, Vicxvectaddr0, Vicxvectaddr1 – Cirrus Logic EP93xx User Manual
Page 177: Vicxvectaddr2, Vicxvectaddr3, Vicxvectaddr4, Vicxvectaddr5, Vicxvectaddr6
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Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
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If you are not using the priority level in the VIC, write the VICxVectAddr
register with any value (in order to disable the interrupt priority) at the
beginning of your program.
It is not always clear when the ARM debuggers read the VICxVectAddr
register, so it is recommended that if you are using a debugger, do not read
the VIC registers via a memory window. If you must read the VIC registers,
read only the VIC registers that are needed.
Bit Descriptions:
VectorAddr:
Contains the address of the currently active ISR. Any
writes to this register clear the interrupt.
VICxDefVectAddr
Address:
VIC1DefVectAddr: 0x800B_0034 - Read/Write
VIC2DefVectAddr: 0x800C_0034 - Read/Write
Definition:
Default Vector Address Register. The VICxDefVectAddr register contains the
default ISR address.
Bit Descriptions:
DefaultVectorAddr: Contains the address of the default ISR handler.
VICxVectAddr0
VICxVectAddr1,
VICxVectAddr2,
VICxVectAddr3,
VICxVectAddr4,
VICxVectAddr5,
VICxVectAddr6
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DefaultVectorAddr
15
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13
12
11
10
9
8
7
6
5
4
3
2
1
0
DefaultVectorAddr