Cirrus Logic EP93xx - Manual (Page 374)

9-72 DS785UM1
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
RXDQBLen
Address:
0x8001_0094 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Descriptor Queue Base Length register. The Receive Descriptor
Queue Base Length defines the actual number of bytes in the receive
descriptor queue, which thereby sets the number of receive descriptors that
can be supplied to the MAC. The length should be set at initialization time and
must define an integral number of receive descriptors.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RDBL: Receive Descriptor Base Length.
RXDQCurLen
Address:
0x8001_0096 - Read/Write. Note half word alignment.
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDBL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDCL