Cirrus Logic EP93xx - Manual (Page 731)

DS785UM1 23-19
Copyright 2007 Cirrus Logic
Synchronous Serial Port
EP93xx User’s Guide
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Definition:
The interrupt status is read from the SSP interrupt identification register
(SSPIIR). A write of any value to the SSP interrupt clear register (SSPICR)
clears the SSP receive FIFO overrun interrupt. Therefore, clearing the RORIE
bit in the SSPCR1 register will also clear the overrun condition if already
asserted. All the bits are cleared to zero when reset.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RORIS: Read: SSP Receive FIFO overrun interrupt status
0 - SSPRORINTR is not asserted.
1 - SSPRORINTR is asserted.
This bit is cleared by writing any value to the SSPSR
register
TIS: Read: SSP transmit FIFO service request interrupt status
0 - SSPTXINTR is not asserted indicating that the transmit
FIFO is more than half full.
1 - SSPTXINTR is asserted indicating that the transmit
FIFO is less than half full (space available for at least four
half words).
RIS: Read: SSP receive FIFO service request interrupt status
0 - SSPRXINTR is not asserted indicating that the receive
FIFO is less than half full.
1 - SSPRXINTR is asserted indicating that the receive
FIFO is more than half full (4 or more half words present in
FIFO)