Vicxsoftint, Vicxintenclear – Cirrus Logic EP93xx User Manual
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DS785UM1
Copyright 2007 Cirrus Logic
Vectored Interrupt Controller
EP93xx User’s Guide
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Definition:
Interrupt Enable Register. The VICxIntEnable register enables the interrupt
requests by unmasking the interrupt sources. On reset, all interrupts are
disabled (masked).
Bit Descriptions:
IntEnable:
Enables the interrupt request lines:
1 - Interrupt enabled. Allows interrupt request to ARM
Core.
0 - Interrupt disabled.
VICxIntEnClear
Address:
VIC1IntEnClear: 0x800B_0014 - Write Only
VIC2IntEnClear: 0x800C_0014 - Write Only
Default: Don’t Care
Definition:
Interrupt Enable Clear Register. The VICxIntEnClear register clears bits in the
VICxIntEnable register.
Bit Descriptions:
IntEnable Clear:
Clears bits in the VICxIntEnable register. Writing a bit to
“1” clears the corresponding bit in the VICxIntEnable
register. Any bits written to “0” have no effect.
VICxSoftInt
Address:
VIC1SoftInt: 0x800B_0018 - Read/Write
VIC2SoftInt: 0x800C_0018 - Read/Write
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IntEnable Clear
15
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2
1
0
IntEnable Clear
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SoftInt
15
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1
0
SoftInt