Cirrus Logic EP93xx - Manual (Page 713)

DS785UM1 23-1
Copyright 2007 Cirrus Logic
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Chapter 23
23 Synchronous Serial Port
23.1 Introduction
The Synchronous Serial Port (SSP) is a master or slave interface for synchronous serial
communication with slave peripheral devices that have either Motorola
® SPI, National
Semiconductor ® Microwire ™ , or Texas Instruments ® synchronous serial interfaces.
The SSP performs serial-to-parallel conversion on data received from a peripheral device.
The CPU or DMA reads and writes data and control and status information. The transmit and
receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to
be stored independently in both transmit and receive modes. Serial data is transmitted on
SSPTXD and received on SSPRXD.
23.2 Features
Following is a list of features of the Synchronous Serial Port.
• Master or Slave operation
• Programmable clock bit rate and prescaler
• Separate transmit and receive FIFO memory buffers, 16-bits wide, 8 locations deep
• Programmable data frame size from 4 to 16 bits
• Independent masking of transmit FIFO, receive FIFO and receive overrun interrupts
The SSP has a programmable choice of interfaces: SPI, Microwire, or TI synchronous serial.
The features of each of these are listed below.
• SPI features:
• Full duplex, four-wire synchronous transfers
• Programmable clock polarity and phase
• The feature of the National Semiconductor Microwire interface is:
• Half duplex transfer using 8-bit control message
• Texas Instrument synchronous serial interface features:
• Full duplex four-wire synchronous transfer
• Transmit data pin can be in high impedance state when not transmitting