Cirrus Logic EP93xx - Manual (Page 379)

DS785UM1 9-77
Copyright 2007 Cirrus Logic
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9
9
9
Definition:
Receive Status Queue Current Length. The Receive Status Queue Current
Length defines the number of bytes between the Receive Status Current
Address and the end of the receive status queue. This value is used internally
to wrap the pointer back to the start of the queue. The register should not
normally be written to.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RSQCL: Receive Status Queue Current Length.
RXStsQCurAdd
Address:
0x8001_00A8 - Read/Write
Chip Reset:
0x0000_0000
Soft Reset:
Unchanged
Definition:
Receive Status Queue Current Address. The Receive Status Queue Base
Address defines the system memory address of the receive status queue.
This address is used by the MAC to reload the Receive Status Queue Current
Status Address whenever the end of the status queue is reached. The base
address should be set at initialization time and must be set to a word aligned
memory address.
Bit Descriptions:
RSQCA: Receive Status Queue Current Address.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSQCA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSQCA