Cirrus Logic EP93xx - Manual (Page 620)

17-24 DS785UM1
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
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EN: Enable value:
00 - No encoder selected
01 - SIR, 0 to 0.1152Mbit/s data rate, using the UART2
interface
10 - MIR, 0.576 or 1.152Mbit/s data rate, using IrDA
interface
11 - FIR, 4.0Mbit/s data rate, using IrDA interface.
Note: While the FIR transmit section is enabled, the FD bit is low, and while the MIR transmit
section is enabled, the MD bit is low. In FIR mode, the FD bit does not go high until the TXE
bit in the IrCtrl register is cleared, and in MIR mode, the same bit must be cleared for MD to
go high. Monitor the TBY bit in the IrFlag register to discover whether a packet is fully
transmitted before clearing TXE.
IrCtrl
Address:
0x808B_0004
Default:
0x0000_0000
Definition:
IrDA Control Register. This register selects various operating parameters.
Note that the RXE and TXE bit must be cleared before selecting a different
interface with the IrEnable register EN bits. The other bits in this register may
be changed while the interface is active.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
AME: Address Match Enable.
0 - Disable receiver address match function, store data
from all incoming frames in the receive buffer.
1 - Enable receiver address match function, do not buffer
data unless address is recognized or incoming address
contains all ones.
RXP: Receive Polarity Control.
0 - Data input is not inverted before decoding.
1 - Data input is inverted before decoding.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD AME RXP TXP RXE TXE TUS BRD 0