Cirrus Logic EP93xx User Manual
Page 587
DS785UM1
16-11
Copyright 2007 Cirrus Logic
UART3 With HDLC Encoder
EP93xx User’s Guide
1
6
1
6
16
TIS:
Transmit Interrupt Status. This bit is set to 1 if the
UARTTXINTR transmit interrupt is asserted, which occurs
when the transmit FIFO is not full. It is set to 0 when the
transmit FIFO is full.
RIS:
Receive Interrupt Status. This bit is set to 1 if the
UARTRXINTR receive interrupt is asserted, which occurs
when the receive FIFO is not empty. It is set to 0 when the
receive FIFIO is empty.
MIS:
Modem Interrupt Status. This bit is set to 1 if the
UARTMSINTR modem status interrupt is asserted. This
bit is cleared by writing any value to this register.
UART3LowPwrCntr
Address:
0x808E_0020 - Read/Write
Default:
0x0000_0000
Definition:
UART3 IrDA Low Power Divisor Register. This register is present in UART3
but is not supported.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
UART3DMACtrl
Address:
0x808E_0028 - Read/Write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RSVD
DMAERR
TXDMAE
RXDMAE