3 dspsc register, 3 dspsc register -10 – Cirrus Logic EP93xx User Manual
Page 80
3-10
DS785UM1
Copyright 2007 Cirrus Logic
MaverickCrunch Co-Processor
EP93xx User’s Guide
3
3
3
cfldrs c3, [r2], #4 ; c3 = *filter++;
cfmuls c1, c2, c3 ; c1 = c2 * c3;
cfadds c0, c0, c1 ; sum += c1;
subs r12, r12, #4 ; j -= 4;
bne inner_loop ; branch if j != 0
sub r0, r3 ; data -= m * 4;
cfstrs c0, [r0], #4 ; *data++ = sum;
sub r2, r3 ; filter -= m * 4;
subs r1, r1, #4 ; n -= 4;
bne outer_loop ; branch if n != 0
mov pc, lr ; return to caller
3.3 DSPSC Register
Default:
0x0000_0000_0000_0000
Definition:
MaverickCrunch Status and Control Register. Accessed only via the
MaverickCrunch instruction set. All bits, including status bits, are both
readable and writable. This register should generally be written only using a
read-modify-write sequence.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
INST:
Exception Instruction. Whenever an unmasked exception
occurs, these 32 bits are loaded with the instruction that
caused the exception. Hence, this contains the instruction
that caused the most recent unmasked exception.
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
INST
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
INST
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DAID
HVID
RSVD
ISAT
UI
INT
AEXC
SAT[1:0]
FCC[1:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
V
FWDEN
Invalid
Denorm
RM[1:0]
IXE
UFE
OFE
RSVD
IOE
IX
UF
OF
RSVD
IO