Cirrus Logic EP93xx - Manual (Page 771)

DS785UM1 27-1
Copyright 2007 Cirrus Logic
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Chapter 27
27 IDE Interface
27.1 Introduction
Note: This chapter applies only to the EP9312 and EP9315 processors.
The IDE interface provides an industry standard connection to ATA/ATAPI compliant devices.
A single IDE port is provided which will attach to master or slave devices. The interface will
support up to:
• 2 Devices
• PIO Mode 4
• Multi-word DMA Mode 2
• Ultra DMA Mode 4
The IDE block will use the internal DMA controller to do the data transfers in Multiword DMA
and Ultra DMA modes. The interface will support only 16 bit devices. The data transfer is
always 16-bit wide, even for a non-data transfer in PIO mode, when only the lower 8 bits are
valid.
27.2 Theory of Operation
The IDE host has one request line, DMAide to the DMA controller, used to request DMA
service. It has an external interrupt line, INTRQ, from the device for interrupt service. It also
has an internally generated interrupt signal INTide for reporting internal errors in the IDE host
to the ARM Core.
The IDE port is connected to the external ATAPI device through a 28-pin interface. Of these
28 signals, 25 use dedicated pins, 2 share
EGPIO pins (EGPIO[2] for DMARQ and
EGPIO[15] for DASPn), and the device interrupt request uses one of the INT pins (INT[3]) for
INTRQ.
The IDE interface hardware is composed of several elements: a GPIO like Pin Interface, a
MDMA Transfer State Machine, a UDMA Transfer State Machine, a pair of Read and Write
Data Buffer FIFOs, and a pair of CRC generation circuits.
The interface between the IDE host and the IDE device is defined in Table 27-1 . The column
labeled Type identifies the block associated with the processor pin. The GPIO type indicates
the 2 pins that are shared with the EGPIO block. The INT type indicates the pin using one of
the
INT pins. The NI type indicates an IDE signal that is not supported. All others are
dedicated pins.