Cirrus Logic EP93xx - Manual (Page 427)

DS785UM1 10-33
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
1
0
1
0
10
Example: if BWC = 1010b (indicating 1024 bytes, see
Table 10-9 , below), the DMA relinquishes control of the
bus on completion of the current burst transfer after BCR
values which are within 15 bytes of multiples of 1024.
PW: Peripheral Width. For external DMA transfers, these bits
are used to program the DMA to request byte/half-
word/word wide AHB transfers, depending on the width of
the external device. These bits are not used for software
triggered M2M transfers.
00 - Byte (8 bits)
01 - Half-word (16 bits)
10 - Word (32 bits)
11 - Not used
For word accesses the lower 2 bits of the
source/destination address are ignored.
For half-word accesses the lower bit of the
source/destination address is ignored.
Table 10-9. BWC Decode Values
BWC Bytes
0000 Full DMA transfer completes
0001 16
0010 16
0011 16
0100 16
0101 32
0110 64
0111 128
1000 256
1001 512
1010 1024
1011 2048
1100 4096
1101 8192
1110 16384
1111 32768