Cirrus Logic EP93xx User Manual
Page 425
DS785UM1
10-31
Copyright 2007 Cirrus Logic
DMA Controller
EP93xx User’s Guide
1
0
1
0
10
for Channel Base Addresses
Note:* Write this location once to clear the bit (see Interrupt/Status register description
for which bits this rule applies to).
CONTROL
Address:
Channel Base Address + 0x0000 - Read/Write
Definition:
This is the Channel Control Register. Used to configure the DMA M2M
Channel. All control bits should be programmed before the ENABLE bit is set.
Bit Descriptions:
RSVD:
Reserved. Unknown During Read.
STALLIntEn:
Setting this bit to “1” enables the generation of the STALL
interrupt in the STALL State of the DMA Channel State
machine. Setting this bit to “0” disables generation of the
STALL Interrupt.
SCT:
Source Copy Transfer. This bit is used to set up a block
transfer from 1 memory source location. If SCT = 1, then
one word is read from the source memory location and
copied to a block of memory (the number of destination
locations written to is determined by BCR). If SCT = 0 then
the source address increments as normal after each
successful transfer as determined by the transfer size (this
is the default setting). In order to use this feature the
SAR_BASEx and DAR_BASEx registers must contain
word-aligned addresses - the DMA will ignore the 2 LSB’s
Channel Base Address + 0x0028
SAR_CURRENT1
RO
32
0
Channel Base Address + 0x002C
DAR_BASE0
R/W
32
0
Channel Base Address + 0x0030
DAR_BASE1
R/W
32
0
Channel Base Address + 0x0034
DAR_CURRENT0
RO
32
0
Channel Base Address + 0x0038
Reserved
Channel Base Address + 0x003C
DAR_CURRENT1
RO
32
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
PWSC
NO_HDSK
RSS
NFBintEn
DREQP
RSVD
DACKP
ETDP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ETDP
TM
SAH
DAH
PW
BWC
START
ENABLE
DONEIntEn
SCT
STALLIntEn
Table 10-8. PPALLOC Register Reset Values (Continued)
Offset
Name
Access
Bits
Reset Value