Cirrus Logic EP93xx - Manual (Page 629)

DS785UM1 17-33
Copyright 2007 Cirrus Logic
IrDA
EP93xx User’s Guide
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RFS: Receive buffer Service Request (read only).
0 - Receive buffer is empty or the receiver is discarding
data or the receiver is disabled.
1 - Receive buffer is not empty and the receiver is
enabled, DMA service request signaled.
TAB: Transmit Frame Aborted. Set to “1” when a transmitted
frame is terminated with an abort. This will only occur if the
TUS bit is set in the IrCtrl register. Writing a “1” to this bit
clears it.
TFC: Transmitted Frame Complete. Set to “1” whenever a
transmitted frame completes, whether it is terminated with
a CRC followed by a stop flag or terminated with an abort.
Writing a “1” to this bit clears it.
TFS: Transmit buffer Service Request (read only).
0 - Transmit buffer is full or transmitter disabled.
1 - Transmit buffer is not full and the transmitter is
enabled, DMA service is signaled.
The bit is automatically cleared after the buffer is filled.
MIMR
Address:
0x808B_0084 - Read/Write
Default:
0x0000_0000
Definition:
MIR Interrupt Mask Register.
Bit Descriptions:
RSVD: Reserved. Unknown During Read.
RFL: RFL mask bit. When high, the MIR RFL status can
generate an interrupt.
RIL: RIL mask bit. When high, the MIR RIL status can generate
an interrupt.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSVD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSVD RFL RIL RFC RFS TAB TFC TFS