Cirrus Logic EP93xx User Manual

Page 349

DS785UM1

9-47

1/10/100 Mbps Ethernet LAN Controller

EP93xx User’s Guide

The following procedure will correctly set the SelfCtl register value:

1. Read the value of SelfCtl

2. Clear PSPRS bit in SelfCtl Register.

3. Read/write PHY registers.

4. Restore the old value to SelfCtl.

RWP:

Remote Wake Pin. This bit reflects the current state of the
REMWAKE pin. Following a system power up, caused by
a Remote Wake-up frame being detected by the MAC, this
bit is set.

GPO0:

General Purpose Output 0. This bit directly controls the
GPO[0] pin. A “1” corresponds to a logic high on the pin.

PUWE:

Power Up Wake-up Enable. Setting the Power Up Wake-
up enable bit causes the MAC to enter the remote wake-
up mode, during normal operation (AHB bus powered up).
In this mode all receive frames that pass the destination
address filter are scanned for the remote wake-up pattern
(six bytes of 0xFF followed directly by sixteen consecutive
copies of the Individual address). When this pattern is
detected, the REMWAKE pin is driven high and Remote
Wake-up (Interrupt Status is set).

PDWE:

Power Down Wake-up Enable. Setting the Power Down
Wake-up Enable bit causes the MAC to enter the remote
wake-up mode when the AHB bus is powered down. In
this mode all receive frames that pass the destination
address filter are scanned for the remote wake-up pattern
(six bytes of FFh followed directly by sixteen consecutive
copies of the Individual address). When this pattern is
detected, the REMWAKE pin is driven high, and can be
used to initiate a system power up, the state of the
REMWAKE pin is visible via the Remote Wake Pin bit of
this register.

MIIL:

MII Loopback. Setting the MII Loopback bit causes
transmit data to be diverted back into the receive data path
prior to the MII interface pins, the transmit data does not
appear on the MII bus and the receive data on the MII bus
is ignored. The clock for the transmit and receive data is
derived from the AHB CLK in the loopback mode. It is
strongly recommended that TXCLK and RXCLK come
from a single clock source with minimum skew in order to
ensure the proper operation of the loopback test. For
reliable operation a software reset should be issued when
the MII loopback bit is changed.